The present invention relates to a bus cycle signature system and more particularly to a bus cycle signature system for automatically testing or debugging a central processing unit (CPU) based mother board.
The bus cycle signature system is for use in testing and trouble-shooting PCAT mother boards and other CPU based boards. The bus cycle signature system generates highly repeatable signature words for each node of a known good board which can then be stored in a database for comparison with a suspect board under test of the same type as the known good board for either quality assurance testing purposes or for the purpose of debugging the suspect board by identifying one or more faulty nodes.
Computer mother boards have grown to such a density and complexity that only a few expensive automatic test equipment (ATE) systems on the market can effectively test and trouble-shoot such boards. The mother board uses a CPU and a chipset comprising highly integrated application-specific integrated circuit (ASIC) chips with a small number of other support components. The clock speed of such a board is usually in the range of 33-50 MHz at present and the clock speed of future boards is expected to increase to a frequency of 66 to 100 MHz. Conventional ATE technology uses the following techniques:
1. An open/short circuit test PA1 2. An in-circuit component measurement test PA1 3. A digital in-circuit functional test PA1 means for driving the CPU at its own clock speed; PA1 probe means for providing a first signal from a test point; PA1 sample means to provide a third signal associated with the CPU clock signal; and PA1 storage means to combine the first and the third signals when the second signal is indicative of the CPU performing a bus cycle thereby providing a signature in the storage means of the test point on the CPU based board.
An example of an in-circuit component measurement tester is the Tescon tester and an example of a digital in-circuit functional tester would be the Genrad Teradyne tester.
The open/short test is basically a test to ensure that there are no unintended electrical open circuits or short circuits in a non-populated (bare) printed circuit board (PCB). The open/short test is not suitable for use with a populated board and so alternative methods must be used to test a populated board. PCB manufacturing technology is of a high standard so faults such as open or short circuits in the bare PCB would not normally be expected. However, at a later stage in the manufacturing/production of PCBs, short circuits caused by solder bridges or open circuits caused by components not being soldered properly may result. This type of open/short circuit testing generally uses a bed of nails test fixture for testing and the extent and accuracy of the test depends on the number of test points (pins) provided in the fixture. When surface mount technology is used, the component population density can be very high and the pin pitch and hence the distance between test points is very small. Thus, such bed of nails test fixtures are more difficult to make and more costly. A bed of nails test fixture for a board which receives a plastic quad flat pack (QFP) would present even more difficulties due to the small distances between test points.
An in-circuit component measurement technique is capable of testing a populated board and uses either a three wire or a six wire method to measure the values of passive components such as resistors, capacitors, inductors, diodes and the like. This is a useful technique when applied to analogue boards but very few passive components are required with today's CPU based mother boards so this test method is unsuitable for such an boards.
A further alternative is a digital in-circuit functional test which either utilises back-driving techniques to test individual digital integrated circuits (IC) one at a time or, alternatively, the whole board is driven by the card edge connectors or by input connectors and the output of the board is evaluated when in operation.
Using the back-driving technique, the chip under test is driven by a test signals and the output of the chip is evaluated and compared with the expected response. This method requires separate programmes for each chip on the board which is to be evaluated. Moreover, a specific test programme must be written before custom chips can be tested in this matter. The testing of a mother board comprising many chips also requires knowledge of the complete logic details of each chip to be tested. However, in most cases the logic details of the mother board chipset will not be available. Even if available, it may take a long time before the test programme is ready and the chip may have been revised in this timescale so the test programme may also need to be revised before testing may take place. If such a test programme is readily available, the digital in-circuit function tester may test the chip at a much slower speed then the actual speed of the chip when operating in normal conditions. For example, a chip may be back-driven at a speed in the range of 1 to 5 MHz whereas, the actual operating speed of the chip when in use may be at 33 MHz. Thus, such a test does not give an indication of the actual performance of the board under its normal operating conditions. Generally, the faster the back-driving speed required, the more expensive the tester becomes.
The alternative method for digital in-circuit functional testing involves driving the board by the card edge connectors or by input connectors. This is called an inboard functional test. Using this method, it is possible to test a board at high operating speeds but, again, it is necessary to write a specific test programme for each type of board to be tested. Additionally, in the case of CPU based boards, it is necessary to synchronise the CPU on the board under test with the inboard functional tester.
Accordingly, the present invention proves an apparatus for testing a CPU based board having a plurality of test points and at least one clock producing a CPU clock signal, which apparatus comprises:
means to provide a second signal indicative of the CPU performing a bus cycle;